27
FN6808.3
October 1, 2009
Device Test
The KAD5512HP can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing. A
static word can be placed on the output bus, or two different
words can alternate. In the alternate mode, the values
defined as Word 1 and Word 2 (as shown in Table 15) are
set on the output bus on alternating clock phases. The test
mode is enabled asynchronously to the sample clock,
therefore several sample clock cycles may elapse before the
data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 16.
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
TABLE 15. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST
MODE
WORD 1
WORD 2
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
0110
Reserved
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
KAD5512HP
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